PURPOSE: To constitute an up/down counter circuit which removes restrictions on input timings of an addition pulse Pu and a subtraction pulse Pd so that it does not matter if both of these pulses overlap and always accurately outputs the difference between numbers of pulses of both of them or a difference signal indicating this difference.

CONSTITUTION: Johnson counters 10 which feed back complementary signals in last stages to initial stages are used as an up counter 1u and a down counter 1d, and coincidence or non-coincidence between corresponding stage outputs X1u to Xnu and X1d to Xnd of both of counters 1u and 1d is examined by an examination means 20 consisting of plural exclusive OR gates 21 to 2n, and the differences between numbers of addition pulses Pu and subtraction pulses Pd received by up and down counters 1u and 1d after reset are detected by the number of outputs showing the same logical state of '1' or '0' out of examination outputs Y1 to Yn and are outputted as difference signals D0 to Dn through a logic circuit means 30 or the like.