Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CPU HAVING MULTIPLE BOOT PROCEDURES
Document Type and Number:
Japanese Patent JP2011180819
Kind Code:
A
Abstract:

To prepare a plurality of boot procedures and prevent malicious device alterations.

A CPU includes a determination circuit including an NMOS transistor 601 that has a first end connected to a power line VDD and a second end connected with an input terminal and switches power from VDD to a third end in response to Input A 600 from the input terminal, an electrical fuse 602 that is connected to the third end of the NMOS transistor 601 and becomes conductive when a voltage is applied for a fixed time from VDD upon the switching, a resistor 603 that has one end connected to the electrical fuse 602 and the other end earthed, and an output terminal that is disposed between the electrical fuse 602 and the resistor 603. If there is no executable code on memory upon power input, Input A 600 is input into the input terminal of the determination circuit, the level of Output 604 from the output terminal is determined at the input, and executable code is obtained from a serial interface and started if Output 604 is low.


Inventors:
HAYASHI MASAKAZU
Application Number:
JP2010044140A
Publication Date:
September 15, 2011
Filing Date:
March 01, 2010
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06F13/14
Attorney, Agent or Firm:
Michio Nagai
Masao Sekiguchi
Takamasa Nakano