PURPOSE: To generate the signal patterns in sequence while simulating the working of a CPU by generating automatically a signal pattern from an instruction code string by means of an instruction analyzing means and a signal pattern output means.

CONSTITUTION: A CPU simulator 1 is provided with a signal pattern input part 4 to fetch a clock signal 14 and a bus input signal 8. An instruction analysis part 5 analyzes and instruction code 11 through the part 4 and generates the bus information 12 to produce a bus output signal 9. Then a signal pattern output part 6 actually generates the signal 9 with the use of the information 12. Furthermore a timing generating part 7 generates the timing information 10 by means of a synchronous signal 13 obtained through the part 4 to secure the action timing of the part 5 and a signal pattern output part 6 respectively. In such a constitution, the CPU signal patterns are generated in sequence together while reflecting the logical simulation result.