PURPOSE: To erase an image fast without placing any load on a microprocessor by supplying erasure data to respective display memories simultaneously in a period wherein data of at least one image plane are read out of plural display memories by a CRT controller.

CONSTITUTION: When the image is erased, zero data generated by a resistance 9 are written in the display memories 21-23 at the same time through respective resistances 31-33 of a data composing circuit 3. During this period, the microprocessor 1 need not to write zero data in the display memories 21-23. Consequently, the load on the microprocessor 1 is reduced correspondingly and the microprocessor can perform other processes. Further, the zero data is written in the display memories 21-23 in one cycle of a vertical synchronizing signal V, so screen erasure is speeded up.