CRYSTALLINE SILICON DIE ARRAY AND METHOD FOR ASSEMBLING CRYSTALLINE SILICON THIN FILM ON SUBSTRATE

Title:

CRYSTALLINE SILICON DIE ARRAY AND METHOD FOR ASSEMBLING CRYSTALLINE SILICON THIN FILM ON SUBSTRATE

Document Type and Number:

Japanese Patent JP2004260170

Kind Code:

A

Abstract:

To provide a crystalline silicon die array on a substrate having a maximum area of 2 m2, and to provide a method for manufacturing the array.

The method for manufacturing the array comprises a process 1202 of describing an array of a die area on a crystalline semiconductor wafer; a process 1204 of implanting hydrogen ions in the die area; a process 1208 of forming a polymer layer so as to cover each die and forming a lamination which includes a die area first wafer layer; a process 1210 of polymerizing and coupling translucent carriers with the die area; a process 1212 of inducing breakage in the wafer by thermal annealing; a process 1214 of sequentially forming a wafer laminate second layer having a narrower layer thickness than that of the die for each die; and a process 1218 of adhering the wafer laminate second layer smoothly to the substrate.

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Inventors:

TAKATO YUTAKA
FLORES JAMES S
DROES STEVEN R

Application Number:

JP2004042608A

Publication Date:

September 16, 2004

Filing Date:

February 19, 2004

Export Citation:

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Assignee:

SHARP KK

International Classes:

G02F1/1345; H01L21/02; H01L21/336; H01L21/44; H01L21/78; H01L23/495; H01L27/12; H01L27/146; H01L29/786; (IPC1-7): H01L27/12; G02F1/1345; H01L21/336; H01L29/786

Domestic Patent References:

JPH11312811A	1999-11-09
JP2002182580A	2002-06-26
JP2001244444A	2001-09-07
JP2002231909A	2002-08-16
JPH11142878A	1999-05-28
JP2001332383A	2001-11-30
JPH10233352A	1998-09-02
JPH07254690A	1995-10-03
JP2002170942A	2002-06-14
JP2002353424A	2002-12-06
JP2002009291A	2002-01-11

Foreign References:

WO2003010825A1	2003-02-06
WO2002084721A2	2002-10-24
WO2002071475A1	2002-09-12
WO2001093325A1	2001-12-06

Attorney, Agent or Firm:

Hiroshi Maeda
Hiroshi Koyama
Yuji Takeuchi

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