Title:
CURRENT MIRROR CIRCUIT
Document Type and Number:
Japanese Patent JPH04168328
Kind Code:
A
Abstract:
PURPOSE:To enable the maintaining of an input impedance at a low level by providing a first current mirror circuit for deriving a plurality of outputs from one input with a second current mirror circuit and an input impedance stabilization means. CONSTITUTION:As an input terminal 7 is a virtual earth point of an amplifier 10, an input impedance RIN is almost zero. A second current mirror circuit made up of NPN transistors Tr21 and Tr22 is arranged and respective collector currents Ic (Tr21) and Ic (Tr22) are equal. In a relationship of a bias current of the amplifier 10, currents I14 and I15 flowing through terminals 14 and 15 of the amplifier 10 are equal by an imaginal shortcircuiting. Therefore, I14-Ic(Tr21)=0 is given and a bias current at an inversion terminal 14 is canceled by the bias current at a non-inversion terminal 15. This enables the suppression of possible offset current in a first current mirror circuit composed of NPN Tr 11 and 22 thereby realizing a current mirror circuit of a low input impedance.
Inventors:
HOMITSU MASATOSHI
Application Number:
JP29392790A
Publication Date:
June 16, 1992
Filing Date:
October 31, 1990
Export Citation:
Assignee:
OLYMPUS OPTICAL CO
International Classes:
G01J1/44; H03F3/08; H03F3/343; (IPC1-7): G01J1/44; H03F3/08; H03F3/343
Attorney, Agent or Firm:
Atsushi Tsuboi (2 outside)