Title:
INTERNAL POWER SOURCE SWITCHING CIRCUIT FOR SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3119740
Kind Code:
B2
Abstract:
PURPOSE: To make the waiting time from a read-out mode to a write-in mode minimize and to obtain the high-speed operation of a circuit by providing a 4th MOS transister having a 1st polarity where one of a drain electrode or a source electrode is connected to a 3rd power swource line and other is connected to a 2nd power spurce line.
CONSTITUTION: MOS transisters (Tr) Q1 to Q4 and power source line 1 to 3 are connected respectively as shown in the figure and an electrical potential VPP is set to a higher voltage than an electrical potential VCC. On the midway for shifting from the read-out mode to the write-in mode, the electrical potential of the power source 2 is brought up to a higher voltage VCC and the transmitted to a node N1 via TrQ3 being ON when a TrQ4 goes to ON. Thus, the channel of a TrQ2 is suppressed since a potential difference between the node N1 and VPP is lowered and the channel current capability of a TrQ3 is increased since the potential difference between a signal G1 and N1 is enlarged. Thus, the occurrence of a latch-up phenomenon is prevented since the income and expense with the channel current of the TrQ3 are balanced. Therefore, the waiting time at the of the mode-shifting is minimized and the high-speed operation in the circuit is obtained.
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Inventors:
Tetsuji Takeguchi
Application Number:
JP29998792A
Publication Date:
December 25, 2000
Filing Date:
November 10, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C17/00; G11C16/06; (IPC1-7): G11C16/06
Domestic Patent References:
| JP4141894A | ||||
| JP4106796A | ||||
| JP2116095A | ||||
| JP23193A | ||||
| JP63244500A |
Attorney, Agent or Firm:
Gunichiro Ariga