PURPOSE: To mount a multi-stage counter or a register circuit with a set or reset terminal having a small area into an integrated circuit chip by fixing an output in the initial state with small number of transistors (TRs).

CONSTITUTION: Transmission gates 6, 9, 11, 14 in the inside of the flip-flop circuit are all turned off by setting clock signals CLK(1), CLK(2)3 to be in phase, e.g. setting a high level to both the clock signals. In this state, N-channel TRs 10, 15 are turned on by setting a level of a line ENB4 to a high level, and a master side output (output of inverter 7) and a slave side output Q18 are respectively fixed to a high level and a low level. Then the level of the line ENB4 is set to a low level to turn off the N-channel TRs 10, 15 and when the clock signal CLK(2)3 is set to a low level, the transmission gates 6, 14 are turned on and a Q output 18 of the flip-flop is kept to be a low level and a clock of an inverted phase is inputted as the CLK(2)3.