Title:
ダマシン・ダブルゲート・トランジスタ及びこれに関連する製造方法
Document Type and Number:
Japanese Patent JP2004517466
Kind Code:
A
Abstract:
This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.
Inventors:
Stefan A Park
Application Number:
JP2002524200A
Publication Date:
June 10, 2004
Filing Date:
August 29, 2001
Export Citation:
Assignee:
Boise State University
International Classes:
H01L21/336; H01L21/84; H01L27/12; H01L29/10; H01L21/768; H01L29/423; H01L29/49; H01L29/51; H01L29/78; H01L29/786; H01L21/28; (IPC1-7): H01L29/78; H01L21/336; H01L21/768; H01L29/786
Attorney, Agent or Firm:
Kosaku Sugimura