To provide data arithmetic circuits which operate at high speed with low power consumption without increasing the number of signal lines.

A data control circuit 11 operates the logical OR between a data signal D1 and an output enable signal 0E by an arithmetic circuit 111, operates the AND between the arithmetic output and a data enable signal DE1, controls a buffer 112 which has output control through the arithmetic output and selectively outputs the data signal D1. A data control circuit 12 operates only the AND between a data signal D2 and the data enable signal DE1 by an arithmetic circuit 121, controls a buffer 122 which has output control through the arithmetic output and selectively outputs the data signal D2. An output circuit 13 synthesizes outputs of each circuits 11 and 12 and outputs a synthetic data signal D3 through a line that is grounded by capacitor 131.