Title:
SERIAL/PARALLEL DATA CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPH0993141
Kind Code:
A
Abstract:
To attain serial/parallel conversion by converting plural serial data received with a clock signal into plural parallel data and outputting superimposingly sequentially by providing a time difference to parallel data.
The conversion circuit has a shift register 1 generating an output enable signal superimposed corresponding to sequentially consecutive bits based on a clock signal, a data distribution circuit generating a data string of plural number depending on the superimposition based on serial data and plural gate circuits 5. Then an individual output enable signal and a data string for each of plural orders corresponding to them individually are given to the gate circuits 5.
Inventors:
SAITO MASANORI
SHIMOMICHI YOICHI
HAYASHI SEIICHI
SHIMOMICHI YOICHI
HAYASHI SEIICHI
Application Number:
JP24731895A
Publication Date:
April 04, 1997
Filing Date:
September 26, 1995
Export Citation:
Assignee:
HITACHI ELECTRONICS
International Classes:
H03M9/00; (IPC1-7): H03M9/00
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