Title:
DATA CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JP3914151
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a data converting circuit which performs row-address pipe-line operation in accessing different row addresses so as to achieve high speed access.
SOLUTION: A data converting circuit converting parallel data of a plural of bits read out from a memory cell section to serial data has a selector control section generating a control signal based on burst length information and address information, and a selector section receiving parallel data of a plural of bits, selecting the prescribed number out of the plural of bits based on the control signal, and outputting the selected bit in serial.
Inventors:
Shinya Fujioka
Taguchi Masao
Fujieda Kazuichiro
Yasuharu Sato
Takaaki Suzuki
Aikawa Tadao
Takayuki Nagasawa
Taguchi Masao
Fujieda Kazuichiro
Yasuharu Sato
Takaaki Suzuki
Aikawa Tadao
Takayuki Nagasawa
Application Number:
JP2002376744A
Publication Date:
May 16, 2007
Filing Date:
June 03, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/407; G11C11/401; G11C11/409; G11C11/4096; (IPC1-7): G11C11/407
Domestic Patent References:
| JP6318391A | ||||
| JP7098981A | ||||
| JP8212778A | ||||
| JP6267279A | ||||
| JP10255476A |
Attorney, Agent or Firm:
Tadahiko Ito
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