Title:
DATA INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JP3456912
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent malfunction of the title circuit that can easily realize data interface by having only to receive data even when a noise or a hazard signal is superimposed on a clock signal.
SOLUTION: This circuit 10 is provided with a serial IN/parallel OUT shift register (SI/PO)11, a 1 μs detector 12 that detects that a data input terminal DATA is set to an 'L' level for a prescribed time, a counter 13 that counts the number of received data, an AND gate 14, and an RS flip-flop consisting of OR gates 15, 16, of an inverter 17 and of a D flip-flop 18, and an OR gate 19. When the 1 μs detector 12 detects that the data input terminal DATA is set to an 'L' level for a prescribed time, the SI/PO 11 can receive a shift clock SCK until the counter 13 counts 8-bit data by using an output at the detector 12 for a data reception start signal.
Inventors:
Kenjiro Matoba
Application Number:
JP36589398A
Publication Date:
October 14, 2003
Filing Date:
December 24, 1998
Export Citation:
Assignee:
Oki Micro Design Co., Ltd.
Oki Electric Industry Co., Ltd.
Oki Electric Industry Co., Ltd.
International Classes:
G06F5/00; G06F5/06; G06F5/12; H03M9/00; (IPC1-7): H03M9/00; G06F5/00; G06F5/06
Domestic Patent References:
| JP57190420A | ||||
| JP5983243A | ||||
| JP59133757A |
Attorney, Agent or Firm:
Minoru Maeda