Title:
DATA PROCESSOR HAVING PLURAL PIPELINE PROCESSING MECHANISMS
Document Type and Number:
Japanese Patent JP3721780
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To input the subsequent register arithmetic instructions to an arithmetic pipeline and to execute them even while the memory access arithmetic instructions are being executed by expanding these access arithmetic instructions within a memory access pipeline.
SOLUTION: The meanings of instructions which are stored in an instruction buffer 1 are analyzed by an instruction decoding unit 2. The register arithmetic instructions are sent to an RS(reservation station) 5 that is placed on the arithmetic pipeline side, and the memory access arithmetic instructions are sent to an RS 4 on the memory access pipeline side. The RS 5 on the arithmetic pipeline side executes the arithmetic instructions whose data dependent relations are eliminated regardless of the memory access arithmetic instructions which are sent to the memory access pipeline side. The instructions of the RS 4 on the memory access pipeline side are sent to an address calculation unit 6. The unit 6 analyzes the meanings of the received instructions and also calculates a memory address to be accessed based on a register and its immediate value.
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Inventors:
Mariko Sakamoto
Application Number:
JP11061698A
Publication Date:
November 30, 2005
Filing Date:
April 21, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP4313121A | ||||
| JP6332701A |
Attorney, Agent or Firm:
Junichi Yokoyama