PURPOSE: To attain the pipeline transfer of data and to speed up the transfer by applying the same addressing to plural internal memories, executing the external transfer of data only through a bus and specifying an address to external data.
CONSTITUTION: A control part 3 transfers the data of the internal memories 4, 5 specified by an address arithmetic part 2 to the external or an arithmetic part 6 and controls the storage of data inputted from the external to the memories 4, 5. When executing arithmetic operation, the memories 4, 5 are respectively selected and controlled so that the data of the memory 4 are transferred to the arithmetic part 6 to use the memory 4 for reading and the operated result is stored in the memory 5 to use the memory 5 for writing. In addition, the control part 3 executes control so that the computed data are written in the memory 4 and outputted to the external through the bus 8 and external data are stored in the memory 5. Consequently, data processing can be executed through the pipeline and general data processing can rapidly be executed.
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FUJII SHIGERU
KUREIGU BERU
