PURPOSE: To have an access to a main register at a speed set before an over- sampling process by providing a main register and a secondary register to write the prescribed spare data to the secondary register and reading selectively the main register in a read mode set immediately after the main register is written and otherwise reading selectively the secondary register respectively.

CONSTITUTION: A main register 2 receives data from an internal data bus 1 and holds them with the 1st control signal (a) of a write control circuit 4. A secondary register 3 receives the spare data and holds them with the 2nd write control signal (b). When a read clock signal (ck) is received, the circuit 4 drives an output selecting circuit 5 and controls a multiplexer 6 to send the output of the register 2 or 3 to an output gate circuit 7. The output of the register 2 is transmitted only in a reading clock mode set immediately after data are written to the register 2.