Title:
DATA SLICE CIRCUIT
Document Type and Number:
Japanese Patent JP3833115
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a data slice circuit capable of precisely binarizing a demodulation signal.
SOLUTION: This data slice circuit is provided with a slice level preparator for preparing and outputting a slice level for slicing a demodulation signal based on the demodulation signal, a comparator circuit having first and second input terminals for comparing the demodulation signal to be inputted from the first input terminal with the slice level to be outputted from the slice level preparator, a data slicer for binarizing and outputting the demodulation signal, and a level detecting circuit for outputting a control signal for operating the data slicer when the demodulation signal has amplitude within a prescribed range.
Inventors:
Nakano Yoshiaki
Yuki Yoneo
Yuki Yoneo
Application Number:
JP2001401330A
Publication Date:
October 11, 2006
Filing Date:
December 28, 2001
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H04L25/03; H04L27/38; (IPC1-7): H04L25/03; //H04L27/38
Domestic Patent References:
| JP6046051A | ||||
| JP10136030A | ||||
| JP10215285A |
Attorney, Agent or Firm:
Yusuke Hiraki
Previous Patent: PRINTING CONTROL SYSTEM AND PRINTING CONTROL METHOD
Next Patent: ビフェニル誘導体、その製法及び薬剤としての使用
Next Patent: ビフェニル誘導体、その製法及び薬剤としての使用