PURPOSE: To transfer a large amount of data between a main memory and an input/output device smoothly by recognizing the number of data to be transferred from the input/output device previously before the data are transferred to the main memory, retrieving the significance of the data, and transferring only necessary data to the main memory.

CONSTITUTION: A sub-memory 13 has plural reception areas wherein received data from the input/output device 8 are held, block by block, before transferred to the main memory and plural transmission areas wherein transmit data to the device 8 are held, block by block. A direct memory access controller 14, on the other hand, performs the DMA transfer of data obtained in the receiving register of a communication control circuit 15 to the memory 13 and also performs the DMA transfer of data in the transmission areas to the transmitting register of the circuit 15. Further, a DMA controller 17 performs the DMA transfer of data from the main memory 5 to the transmission areas of the memory 13 and also performs the DMA transfer of received data held in the reception areas of the memory 13 to the memory 5. Then, a control circuit 26 retrieves the significance of the received data obtained in the reception areas of the memory 13.