PURPOSE: To receive a data at an optional transmission speed by sampling and storing a reception data and reading the data in response to a request of a master set.

CONSTITUTION: A reception data is inputted to a start bit detection circuit 1 and a latch circuit 3. The detection circuit 1 sends a count start signal to an address control circuit 2. The control circuit 2 gives a clock from a clock generator 8 to the latch circuit 3, which latches the reception data. A selector 4 stores the reception data to a memory 5 and outputs the reception data to a bit check circuit 6 from a memory 5. The bit check circuit 6 outputs a reception data to the latch circuit 7 when no error exists and outputs an interruption signal to a CPU of a master set simultaneously. The latch circuit 7 latches the reception data till the CPU of the master set reads the data. The CPU of the master set reads the reception data.