PURPOSE: To reduce the required storage amount of a data transmitter, by bringing the timing of a data receiving timing signal into a low speed when the amount of storage stored temporarily in a memory section exceeds the 1st prescribed value, and bringing it into a high speed when the amount is lower than the 2nd prescribed amount.
CONSTITUTION: The detection 8 of a specific code EOL added after each line is monitored at a control section, and when a part between the EOLs is 1-line minimum transmission time or below, the control section 6 indicates the insertion of a fill bit between a data and the EOL to a fill insertion section 10. The control section 6 monitors the amount of data storage of a memory section 9 and when the amount exceeds a prescribed amount, a clock signal ST2 of the transmission timing from a timing generating section 7 is stopped or decelerated. Thus, the data of the memory section is decreased because the transmission speed toward a line 4 is unchanged. Further, the control section 6 monitors also the direction of data reduction and when the amount is a prescribed amount or below, the control section 6 gives indication to the generating section 7 to be restored to the original communication speed again.
| JP2006270476 | PACKET SORTER |
| JPH0430642 | BUFFER CONTROL SYSTEM |
| JP2009111796 | STREAM DATA PROCESSOR |
AKIYAMA FUMIO
YONEDA ISAO
MOTOHASHI TOMOO
| JPS5250644A | 1977-04-22 | |||
| JPS5819062A | 1983-02-03 | |||
| JPS5082946A | 1975-07-04 | |||
| JPS5215491A | 1977-02-05 |