PURPOSE: To stop the working of a processor having no halt terminal and to realize the insertion and deletion of a debug branch instruction, by giving twice the output instruction for output register to the end of a branch instruction in case an original program is reset after the end of debug.

CONSTITUTION: A subject program of debug is stored in a program memory 1, and the next address is given via a contact A of a switch 6 in response to the decoding result of the preceding instruction of an instruction decoding part 3 of a digital signal processing circuit 9. With this address a new instruction code is given to a DSP main body part 5 and executed. At the same time, a debug processing control part 2 is connected to the memory 1 and an external data processing circuit 7 is connected to an output register 4 of the circuit 9. Then the output instruction for register 4 is given twice to the end of the branch instruction when an original program is reset after the end of debug. Thus the working is stopped for the part 5 having no halt terminal, and the insertion and deletion are possible for the debug branch instruction.