PURPOSE: To perform decimal multiplication at a high speed and with simple hardware constitution, by adding the combined data of the lower and upper digit compnents of the data which is obtained from the multiplication logic for the multiplication table.

CONSTITUTION: The data equivalent to 4 digits to be multiplied of a decimal operand and the multiplication data equivalent to a digit of B of the data are supplied to a multiplication logic 103 for the multilication table. The logic 103 feeds the results of the multiplication table of each digit of the data to be multiplied to a decimal adder circuit 106 after dividing them to the combined data MPY UP0-15 of upper digits and the combined data MPY LOW1-15 of lower digits and by using the above-mentioned data as the input address. The data MPY UP0-15 is compensated and then applied to an adder 108 along with the data MPY LOW0-15 to be added together. The result of this operation is compensated through a circuit 109 and then delivered in the form of a data AS0-15 of the multiplication result of (4×1) digits.