Title:
DECODER FOR CODING SYSTEM WITH HIGH EFFICIENCY FOR TELEVISION SIGNAL
Document Type and Number:
Japanese Patent JPH01198882
Kind Code:
A
Abstract:
PURPOSE:To realize a decoder with simple composition by executing a decoding operation by using a data rearranging circuit based on a simple change in an operation expression and a multiplier. CONSTITUTION:In order to execute the operation of an expression I, the present device is equipped with a data rearranging means 21 to prepare the output data of the prescribed number of bits composed by repeatedly arranging a coding code BPL. Further, the device is equipped with a multiplying means 22 to multiply the output data of the data rearranging means 21 and a dynamic range DR and a means 23 to fetch (the number of the bits of difference data DELTADATA+1) bits from the higher order bit of a multiplied result obtained from the multiplying means 22, round the least significant bit, and decode the difference data DELTADATA. Thus, a decoder corresponding to an EM edge matching having the simple composition can be obtained.
Inventors:
HATTORI MASAYUKI
SHIROTA NORIHISA
SHIROTA NORIHISA
Application Number:
JP2331988A
Publication Date:
August 10, 1989
Filing Date:
February 03, 1988
Export Citation:
Assignee:
SONY CORP
International Classes:
H04N19/60; H04N19/102; H04N19/12; H04N19/136; H04N19/196; H04N19/42; H04N19/44; H04N19/46; H04N19/70; H04N19/91; H04N19/98; (IPC1-7): H04N7/133
Attorney, Agent or Firm:
Sada Ito (1 person outside)
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