To provide a method and a device that eliminates the need of an over-sampling clock used to decode data and timing information.

A method and a device to decode a stream of data that are coded to a chip stream and so as to derive a chip speed and a chip phase of the chip stream from the coded data is explained. This method consists of a step where a clock signal (clk) with a clock speed nearly equal to a tip speed or its integer multiple thereof, a step that gives a tip stream along with a multi-stage delay line 14, a step that samples data of the tip stream in plural stages of the delay line to generate a set of over-samples, a step that generates an estimated position (edgepos) at each set of over-sampling of a chip edge of the chip stream with respect at to each clock period, a step where at least one of over-samples ((dec-chip(0), dec-chip(1)) placed within a limited range with respect to the estimated chip edge position, and a step where the selected over-sample is outputted.