To make any arbitrary data pattern stably synchronize with a reception side clock without using a PLL circuit by latching the signals, which are parallelly outputted after delayed respectively, according to the reception side clock and selecting the signal of an optimum phase for change.
The input data are successively delayed at every delay time shorter than 1/2 cycle by a delay means 1, the delayed data (1)-(8) of different delay time are latched by a latch means 2 by using a clock signal CK, and the change point of '0' and '1' is detected by a differentiating means 3. Based on this change point, latch output data (1)'-(8)' are discriminated, any one of latch output data (1)'-(8)' is selected by a select means 5 based on a select signal from a decoder 4 corresponding to the intermediate position of adjacent and continuous '1' of '0' in (1)'-(8)' and when the select signal from the decoder 4 is equal continuously for prescribed times, the select signal is outputted. When it is less than the prescribed times, the preceding select signal is outputted and latched by the CK.
YAMAUCHI YASUHIRO
SHOJI TOSHIHIRO
OGAWA MASAYUKI
NISHISAKA KIYOMASA
