PURPOSE: To avoid effectively various troubles attended with the use of an analog integration circuit by using two sample-and-hold circuits connected in cascade and applying decoding in quasi-digital way.

CONSTITUTION: A decoding circuit 1 is provided with an input terminal IN receiving a delta modulation signal D outputted from a comparator circuit 2, sample-and-hold circuits 1a, 1b connected in cascade, an adding circuit 1c adding the delta modulation signal C obtained by adding between the delta modulation signal D at the input terminal IN and the output signal B of the sample-and-hold circuit 1b at the post-stage to the sample-and-hold circuit 1a of the pre-stage, and an output terminal OUT from which the output of the sample-and-hold circuit 1a of the pre-stage is applied to one input terminal of the comparator circuit 2 as a decoded output A of the decode circuit 1. The sample-and-hold circuits 1a, 1b are provided with switches S1, S2 switched by clock signals 1, 2 arisen alternately in the same period as the clock (comparison) period of the delta modulation signal D fed to the input terminal IN and perform alternate sampling.