Title:
DELAY COMPENSATION CIRCUIT
Document Type and Number:
Japanese Patent JP3813814
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make a minimum unit in which phase matching can be realized small by a delay compensation circuit.
SOLUTION: This delay compensation circuit is provided with a clock synchronization delay control circuit 10 which has first and second delay lines 23 and 24 composed of a plurality of delay cells 20 having the same configuration and generates a second clock signal whose phase is matched to that of a first clock signal by evaluating delay quantity to be corrected in the first delay line and deciding the number of steps of the delay cells of the second delay line so as to reflect the evaluated delay quantity on the second delay line, and a phase interpolation circuit 11 for generating the second clock signal by mixing the phases of at least two outputs among outputs of the delay cells of the decided number of steps of the second delay line and among outputs that go through the delay cells of the number of steps which is more or less than the decided number of steps.
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Inventors:
Yoshihisa Iwata
Application Number:
JP2000357981A
Publication Date:
August 23, 2006
Filing Date:
November 24, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F1/10; G11C11/407; G11C11/4076; H03K5/00; H03K5/131; H03K5/14; (IPC1-7): H03K5/14; G06F1/10; H03K5/00
Domestic Patent References:
| JP11355262A | ||||
| JP1170113A | ||||
| JP11186903A | ||||
| JP8237091A | ||||
| JP11041095A |
Foreign References:
| WO1999016078A1 |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai