Title:
DELTA-SIGMA MODULATOR
Document Type and Number:
Japanese Patent JP3833548
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a delta-sigma modulator without high-frequency noise or variations of an input full scale voltage depending on the sampling frequency.
SOLUTION: A selection circuit 12 selects an input analog signal and an output signal from a passive low-pass filter 11. A first switched capacitor circuit 13 samples selected signals at the selecting circuit 12. A second switched capacitor circuit 14 samples a reference signal. A integrator 15 integrates both sampled signals sampled by the first switched capacitor circuit 13 and the second switched capacitor circuit 14. A quantizer 16 outputs a digital signal obtained by quantizing the output signal of the integrator 15. A feedback circuit 17 controls the output signal of the second switched capacitor circuit 14, when the output signal is inputted to the integrator 15 so that the output signal is not inverted or inverted, according to the output signal of the quantizer 16.
Inventors:
Ken Yamamura
Application Number:
JP2002051769A
Publication Date:
October 11, 2006
Filing Date:
February 27, 2002
Export Citation:
Assignee:
Asahi Kasei Microsystem Co., Ltd.
International Classes:
H03M3/02; (IPC1-7): H03M3/02
Domestic Patent References:
| JP6291667A | ||||
| JP7106975A | ||||
| JP8018457A | ||||
| JP3034628A | ||||
| JP8125541A | ||||
| JP1094726A |
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Cui Shu Tetsu
Yoshiaki Naito
Cui Shu Tetsu