Title:
DELTA SIGMA MODULATOR
Document Type and Number:
Japanese Patent JP3845505
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate noise included in an input 1-bit signal without increasing a degree number by allowing the modulator to have a middle stage mixing means and a final stage mixing means in addition to a quantization means and a 1st stage mixing means that obtains an integration value of sums of a product between an input 1-bit signal and a coefficient and a product between an output signal and a coefficient.
SOLUTION: A mixer section of the 1st stage of the modulator has an integration device consisting of an adder 131 and a delay circuit 141. A one-bit coefficient multiplier 121(161) multiplies a coefficient a(A) in p-bit with a 1-bit signal. Each mixer section in the middle stage has an integration device consisting of an adder 132(133) and a delay circuit 142(143). The adder 132(133) adds an output of the delay circuit 142(143) of the preceding state, that is, the integral value of the preceding stage to each output of the 1-bit coefficient multiplier. The final stage is provided with a one-bit coefficient multiplier 124 connecting to an input terminal 11 and adder 134 that adds an output of the one-bit coefficient multiplier 124 and an output of the delay circuit 143.
Inventors:
Easty Peter Charles
Slight Christopher
Soap Peter Damian
Slight Christopher
Soap Peter Damian
Application Number:
JP28083997A
Publication Date:
November 15, 2006
Filing Date:
October 14, 1997
Export Citation:
Assignee:
Sony United Kingdom Limited
International Classes:
H03M7/32; H03H17/04; H04B14/06; (IPC1-7): H03M7/32; H04B14/06
Other References:
F.Harris,B.Caulfield,B.McKnight ,New architectures with distributed zeros for improved noise shaping of delta-sigma analog to digital,Signals, Systems and Computers, 1993. 1993 Conference Record of The Twenty-Seventh Asilomar Conferen,1993年11月,vol.1 ,p.421-425
P.F.Ferguson,Jr.,A.Ganesan,R.W.Adams,One bit higher order sigma-delta A/D converters,Circuits and Systems, 1990., IEEE International Symposium on,1990年 5月,Vol.2,pp.890-893
Peicheng Ju,D.G.Vallancourt,QUANTISATION NOISE REDUCTION IN MULTIBIT OVERSAMPLING Σ-Δ A/D,ELECTRONICS LETTERS,1992年 6月 4日,VOL.28,NO.12,pp.1162-1164
R.W.Adams,T.Kwan,,A monolithic asynchronous sampie-rate converter for digital audio,Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on,1993年 5月,pp.1963-1966
P.F.Ferguson,Jr.,A.Ganesan,R.W.Adams,One bit higher order sigma-delta A/D converters,Circuits and Systems, 1990., IEEE International Symposium on,1990年 5月,Vol.2,pp.890-893
Peicheng Ju,D.G.Vallancourt,QUANTISATION NOISE REDUCTION IN MULTIBIT OVERSAMPLING Σ-Δ A/D,ELECTRONICS LETTERS,1992年 6月 4日,VOL.28,NO.12,pp.1162-1164
R.W.Adams,T.Kwan,,A monolithic asynchronous sampie-rate converter for digital audio,Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on,1993年 5月,pp.1963-1966
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga
Previous Patent: MANUFACTURE OF CORRUGATED CARDBOARD LAMINATE
Next Patent: RECEPTION SIGNAL STRENGTH DISPLAY CIRCUIT
Next Patent: RECEPTION SIGNAL STRENGTH DISPLAY CIRCUIT