Title:
分波回路、合波回路、およびチャネライザ中継器
Document Type and Number:
Japanese Patent JP6745973
Kind Code:
B2
Abstract:
A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.
Inventors:
Yuta Takemoto
Akinori Fujimura
Yuichi Yamamoto
Akinori Fujimura
Yuichi Yamamoto
Application Number:
JP2019504578A
Publication Date:
August 26, 2020
Filing Date:
March 05, 2018
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03H17/00
Domestic Patent References:
| JP2004364027A | ||||
| JP2007312200A | ||||
| JP2014053685A |
Foreign References:
| WO2010064485A1 | ||||
| WO2012026417A1 | ||||
| WO2011065287A1 |
Attorney, Agent or Firm:
Michiharu Soga
Kajinami order
Kazuhiro Oyaku
Shunichi Ueda
Junichiro Yoshida
Kajinami order
Kazuhiro Oyaku
Shunichi Ueda
Junichiro Yoshida