Title:
【発明の名称】強誘電体メモリ
Document Type and Number:
Japanese Patent JPH09508240
Kind Code:
A
Abstract:
A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.
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Inventors:
Takashi Mihara
Watanabe Hitoshi
Hiroyuki Yumori
Paz de Arajo, Carlos A.
Macmillan, Larry Dee.
Watanabe Hitoshi
Hiroyuki Yumori
Paz de Arajo, Carlos A.
Macmillan, Larry Dee.
Application Number:
JP51463095A
Publication Date:
August 19, 1997
Filing Date:
October 26, 1995
Export Citation:
Assignee:
Symmetrics corporation
Olympus Optical Co., Ltd.
Olympus Optical Co., Ltd.
International Classes:
G11C17/00; G11C11/22; G11C16/04; H01L21/8247; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C11/22; G11C16/02; H01L27/10; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Takashi Ishida (3 others)