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Patent Searching and Data


Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6425394
Kind Code:
A
Abstract:

PURPOSE: To actuate with a 5V-single power source by making a writing high voltage and a ground potential in accordance with data to be written to a selected bit line and holding a non-selective word line and a bit line at a pre- charged potential.

CONSTITUTION: At the time of a data writing cycle, first, after the word line and the bit line potential are pre-charged to a re-charged voltage which is a writing preventing voltage, any one out of the writing high voltages the pre- charged voltage and the ground voltage, in accordance with data to be written, the selective word line and the selective bit line potential are set to and other non-selective word line and bit line hold a pre-charged voltage condition in an electrically floating condition. Both of a data erasing (writing '1') and a programming (writing '0') are executed by utilizing a tunnel current through the tunnel insulating film of the transistor of a memory cell. Accordingly, a writing high voltage generation is executed by using the internal pressure rising circuit of an on-chip and the 5V-single action can be executed.


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Inventors:
TERADA YASUSHI
NAKAYAMA TAKESHI
KOBAYASHI KAZUO
Application Number:
JP18269887A
Publication Date:
January 27, 1989
Filing Date:
July 21, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C17/00; G11C16/02; G11C16/08; G11C16/12; G11C16/24; (IPC1-7): G11C17/00
Domestic Patent References:
JPS58115691A1983-07-09
Attorney, Agent or Firm:
Mamoru Takada (1 person outside)