PURPOSE: To provide a MOS transistor excellent in short channel effect and low in junction capacity and suitable for high-speed operation.
CONSTITUTION: A well layer 4, where the maximum value of the concentration of impurities is deeper than that at the surface of a board, is provided below an n-type source and a similar drain 8 and 9, and a highly n-type semiconductor layer 11 is provided between the source and drain 8 and 9 and the well layer 4. To form this n-type semiconductor layer 11 in a self alignment manner, an insulating film sidewall 11 is provided in the vicinity of a gate 6. Hereby, a thick depletion layer is made between the n-type semiconductor layer 11 and a low level doped well region 2, and the junction capacity can be reduced, and it can be speeded up. The margin in positioning becomes needless by self alignment technology.
MIYAMOTO MASABUMI
NAGAI AKIRA
SASAKI YASUHIKO
