Title:
【発明の名称】半導体記憶装置及びデータ処理装置
Document Type and Number:
Japanese Patent JP3228759
Kind Code:
B2
Abstract:
In the peripheral circuit of a static RAM comprised by memory cells (1) of the polysilicon high resistance type, is provided a word line voltage transformation circuit (50) which sets the potential of a selected word line (WL) during writing operation to be the potential VVOL, the value of which is higher than that of the supplied potential VDD. The word line voltage transformation circuit comprises a ring-oscillator circuit, a transformation timing signal generating circuit, a step-up gate control signal generating circuit, a stepped-up potential generating circuit, a word line supplied potential mixing circuit, and a word line potential supply control circuit.
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Inventors:
Hiroshi Kayamoto
Masahiko Nakashima
Masahiko Nakashima
Application Number:
JP240691A
Publication Date:
November 12, 2001
Filing Date:
January 14, 1991
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C11/417; G11C5/14; G11C8/08; G11C11/407; G11C11/41; G11C11/415; G11C11/418; G11C11/419; (IPC1-7): G11C11/417
Domestic Patent References:
| JP23171A | ||||
| JP6085493A | ||||
| JP57172587A |
Attorney, Agent or Firm:
Minoru Yamada