Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3170980
Kind Code:
B2
Abstract:
PURPOSE: To conform to, e.g. the GTL standard sufficiently by providing one external terminal as a reference voltage input terminal, and accurately performing the logical judgment of high-speed small transmission signals having a plurality of bits.
CONSTITUTION: With respect to a plurality of logical, judgment circuit parts 381, 382...38n, one internal reference-voltage generating circuit 42 commonly used for a plurality of the logical judgment circuit parts 381, 382...38n is provided. As a result, a DC bias current flowing through each of the logical judgment circuit parts 381, 382...38n agrees with a DC bias current flowing through the internal reference-voltage generating circuit part 42. Therefore, the DC offset balance between the logical judgment circuits 381, 382...38n and the internal reference-voltage generating circuit part 42 can be achieved and the AC offset can be suppressed at the same time. Thus, the high gain and the input/output characteristic of a high band-width product can be obtained. Especially, the semiconductor integrated circuit suitable for the GTL standard can be obtained.
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Inventors:
Masao Taguchi
Application Number:
JP29766993A
Publication Date:
May 28, 2001
Filing Date:
November 29, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L27/04; G11C11/409; H01L21/822; H03K19/003; (IPC1-7): H01L27/04; H01L21/822
Domestic Patent References:
| JP6057644A | ||||
| JP61223675A |
Attorney, Agent or Firm:
Tetsuo Hirado