Title:
DEVICE INCLUDING LOW POWER TYPE STATIC LOGIC CIRCUIT WITH IMPROVED OUTPUT SIGNAL LEVEL AND MANUFACTURE OF SAME DEVICE AS WELL AS PROCESSING OF LOGIC SIGNAL
Document Type and Number:
Japanese Patent JPH08223026
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To improve an output signal and a level, and to reduce power consumption by selectively applying a voltage bias through a bias circuit in a static logic circuit for applying a backward bias to a pull-up or pull-down transistor. SOLUTION: A static logic inverter circuit 100 is provided with a pull-up amplifier circuit 102 constituted of a pull-up transistor group, and a pull-down amplifier circuit 104 constituted of a pull-down transistor group for receiving an input logic signal IN, and operating a signal node 106 for forming an output signal OUT. IN this case, a voltage bias is selectively applied to the circuit 100 for applying a backward bias to the pull-up transistor group or the pull- down transistor group. As a result, those transistor groups are completely cut off when turned off by the input logic signal IN.
Inventors:
GOTSUDOFUREI POORU DESUUZA
DAGURASU EI READO
DAGURASU EI READO
Application Number:
JP32287395A
Publication Date:
August 30, 1996
Filing Date:
December 12, 1995
Export Citation:
Assignee:
SUN MICROSYSTEMS INC
International Classes:
H03K19/0175; H03K19/003; H03K19/0948; (IPC1-7): H03K19/0948; H03K19/0175
Attorney, Agent or Firm:
Hironobu Onda