To provide a device tester which enables security of pins of a number allottable in response to an increase in the number of DUTs and addition of functions, or efficient selection of inexpensive packages, by reducing the number of required pins of each FPGA.

The device tester performs an electrical test of a DUT 140, and is typically configured by providing a parallel-to-serial conversion section 136 for converting a parallel signal received from a data bus 124 to a serial signal, a serial-to-parallel conversion section 142 for converting the serial signal to a parallel signal, pin controlling FPGAs 138 having relay controllers 148 for outputting relay control signals according to the converted parallel signal, and drive circuits 132 which are controlled by the relay control signals and perform switching of input/output signals to the DUT 140.