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Title:
差動ラッチ回路
Document Type and Number:
Japanese Patent JP4792272
Kind Code:
B2
Abstract:

To solve a problem of a conventional differential latch that an unstable operation begins when an input amplitude gets smaller due to the effect of a high speed operation or the like.

A plurality of threshold values of longitudinally stacked transistors (M1. M3) in the differential latch are used to decrease more a gate-source voltage of the stage (M1) closer to a positive power supply VDD in the longitudinally stacked transistor group and to bring the operation of the transistor (M3) remoter from the positive power supply closer to a saturation region from a linear region thereby extending a range of the input amplitude whereat the transistors can execute switching operations toward a lower amplitude and preventing increase in a consumed current.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
Kiyoshi Miyashita
Application Number:
JP2005303079A
Publication Date:
October 12, 2011
Filing Date:
October 18, 2005
Export Citation:
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Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H03K3/3562; H03K3/356; H03K23/44
Domestic Patent References:
JP2001127596A
JP31713A
JP8250984A
Other References:
武石・原監修,「MOS集積回路の基礎」,日本,(株)近代科学社,1999年 6月10日,初版第3刷,12~13頁,基板バイアス効果
古川清二郎著,「半導体デバイス」,日本,株式会社コロナ社,2004年 6月30日,初版第23刷,164~165頁,MISFETの基板バイアス効果
Attorney, Agent or Firm:
Yoshikazu Tani
Atsuhiro Hamanaka
Nobuyuki Kato