Title:
DIFFERENTIAL LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3523611
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a differential logic circuit to be operated at high speed with a low voltage.
SOLUTION: This circuit is composed of a differential push-pull circuit 10 composed of enhancement type NMOSFETs 11 and 12 and depression type NMOSFETs 13 and 14 and a CMOS inverter couple circuit 20 composed of inverters 21 and 22, and the threshold voltage of an FET in the CMOS inverter couple circuit 20 is made into value equal to or greater than the threshold voltage of the enhancement type FET in the differential push-pull circuit 10 and smaller than almost 1/2 of a power supply voltage.
Inventors:
Douseki, Takakuni
Shimamura, Toshishige
Shimamura, Toshishige
Application Number:
JP2001152716A
Publication Date:
April 26, 2004
Filing Date:
May 22, 2001
Export Citation:
Assignee:
NIPPON TELEGR & TELEPH CORP <NTT>
International Classes:
H03K19/096; H03K3/356; H03K19/0944; (IPC1-7): H03K19/0944; H03K19/096
Attorney, Agent or Firm:
谷 義一 （外１名）
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