PURPOSE: To provide the digital circuit which obtains a stable output independently of the temperature, the element characteristic, and the change of the supply voltage by putting another circuit in a PLL loop.

CONSTITUTION: A pulse generator 61 is provided with a PLL circuit 45 and a timing circuit 46 to which the output of this circuit 45 is inputted. The PLL circuit 45 is a 2-multiplier and has a phase comparator 42, a VCO 43, a 1/2 frequency division circuit 44, a low pass filter, etc., as components. The timing circuit 46 is provided with the delay circuit where plural inverters 62 are connected in series and gate circuits 64 and 65 which use the delay in inverters taken out from each array of inverters to perform the gate processing of signals different by phase relations. The output of the inverter array in the preceding stage of the timing circuit 46, namely, a delay wave CL3 from the inverter 62 in the second stage is inputted to the frequency division circuit 44, and the phase of an outputted frequency-divided wave CL5 and that of an external clock signal CL1 are compared with each other by the comparator 42, and the VCO 43 oscillates so that phases coincide with each other. Thus, the input of the PLL circuit 45 and the phase of the timing circuit 46 are kept fixed.