Title:
COUNTER CIRCUIT AND COUNTER CIRCUIT TEST METHOD
Document Type and Number:
Japanese Patent JPH08186486
Kind Code:
A
Abstract:
PURPOSE: To realize the counter circuit and its test method which can shorten the test time at the time of testing the circuit including the connection state between a carry terminal and the enable terminal of a counter in the next stage.
CONSTITUTION: In the synchronous counter circuit where carry terminals and enable terminals of plural m-bit counters 11, 12,... are connected in series, a first test terminal TESTA connected to only enable terminals of m-bit counters in odd stages out of m-bit counters 11, 12,... connected in series in common and a second test terminal TESTB connected to only enable terminals of m-bit counters in even stages in common are provided independently of each other.
Inventors:
TAKANO HIROSHI
Application Number:
JP32613994A
Publication Date:
July 16, 1996
Filing Date:
December 27, 1994
Export Citation:
Assignee:
NEC CORP
International Classes:
H03K23/40; G01R31/28; (IPC1-7): H03K23/40; G01R31/28
Domestic Patent References:
| JPH04351118A | 1992-12-04 | |||
| JPS59115621A | 1984-07-04 |
Attorney, Agent or Firm:
Takahashi Isamu
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