PURPOSE: To eliminate a waiting state and to accelerate the processing speed of an RISC by generating an address not during a separate address generation cycle but during a decoding cycle generated inside a pipeline type RISC instruction processing.
CONSTITUTION: Reduction instruction set computer(RISC) instructions to be processed are stored in an instruction register 200 as bits a0-a31. At the start of the decoding cycle, the instruction code of the instruction is parallelly sent through a read line 505 as input to a complete decoding circuit 510 and an instruction pre-decoding circuit 520. Then, in order to provide a memory address during the instruction decoding cycle, the complete decoding and pre-decoding of one RISC instruction are both parallelly performed. Thus, the number of the waiting states generated during the pipeline type processing of the RISC instructions is reduced and the speed of a processor is accelerated.
DANIERU TAAJIEN RIN
RICHIYAADO EDOWAADO MATEITSUKU
