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Title:
DIGITAL PHASE SYNCHRONIZING CIRCUIT
Document Type and Number:
Japanese Patent JPH01286522
Kind Code:
A
Abstract:

PURPOSE: To reduce the pull-in time by selecting signals outputted from a variable frequency division means and having a different phase, supplying the result and revising a selected signal in response to the phase difference between an input signal and the selected signal.

CONSTITUTION: The circuit consists of a reference signal generating circuit 10, a programmable frequency divider 11, a selection circuit 12, a phase comparator 13, an up-down counter 14, a 1st detection circuit 15, a 2nd detection circuit 16, and a control circuit 17. A signal among signals having different phases from the variable frequency divider 11 is selected and fed to a phase comparator means 13 to synchronize the selected signal with the input signal. In this case, a phase difference between both the signals is detected and an output of the variable frequency divider 11 selected by the selection circuit 12 is changed in response to the phase difference. Thus, the pull-in time is reduced.


Inventors:
SANO MASAYUKI
Application Number:
JP11544888A
Publication Date:
November 17, 1989
Filing Date:
May 12, 1988
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H03L7/06; (IPC1-7): H03L7/06
Attorney, Agent or Firm:
Takuji Nishino (1 person outside)



 
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