PURPOSE: To extract a clock component from a transmitting signal directly, by using a variable frequency divider, a phase detecting circuit operated at the level change and a control circuit controlling the variable frequency divider.
CONSTITUTION: The frequency dividing ratio of the frequency divider 3 is changed with a signal from a phase detector 1 detecting the phase difference between an input transmitting signal and an output of the frequency divider 3 frequency-dividing a signal from a reference oscillator 4 to phase-lock the input transmitting signal and the output of the frequency divider. The detector 1 is constituted so that the phase difference is detected only when the level change in the input signal exists and the output of the phase difference signal in error from the phase detector 1 is prevented. Otherwise, a circuit 5 which increases/decreases the number of pulses fed to the frequency divider 3 without changing the frequency dividing ratio is usable. Thus, a timing signal is extracted directly not through a tank circuit from the transmission signal. Further, this circuit is suitable for circuit integration.
TAKASAKI YOSHITAKA
NAGANO KATSUYUKI
| JPS5614727A | 1981-02-13 | |||
| JPS56128027A | 1981-10-07 |