Title:
LOGIC LEVEL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPS58205335
Kind Code:
A
Abstract:
A circuit arrangement for level conversion of ECL-logic levels to TTL-logic levels, having an emitter-coupled current switch with an input addressable by ECL-logic levels, and a TTL-logic output stage, includes a voltage-controlled current source having an input addressable by an output of the current switch, and having an output connected to the TTL-logic output stage.
Inventors:
AREKUSANDAA REHINAA
Application Number:
JP7918883A
Publication Date:
November 30, 1983
Filing Date:
May 06, 1983
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H03K19/018; (IPC1-7): H03K19/092
Attorney, Agent or Firm:
Tomimura Kiyoshi