Title:
DIGITAL PLL CIRCUIT AND PHASE SYNCHRONIZATION METHOD
Document Type and Number:
Japanese Patent JP3694639
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a digital PLL circuit and a phase synchronization method that can obtain a recovered carrier signal with high accuracy even under a deteriorated crosstalk environment.
SOLUTION: The PLL circuit and the phase synchronization method of this invention are configured such that when a crosstalk wave exists in the vicinity of a frequency of an extracted complex carrier signal, 4-input selector circuits 60a, 60b discriminate whether or not a lock state is finished according to data from a mean value discrimination circuit or a fluctuation value averaging circuit, and select a state of the digital PLL circuit so that a storage coefficient is multiplied with a phase error when the lock state is finished and the result is outputted or a lock coefficient is multiplied with the phase error when the lock state is not finished and the result is outputted.
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Inventors:
Mitsuo Kubo
Application Number:
JP2000224846A
Publication Date:
September 14, 2005
Filing Date:
July 26, 2000
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H04N5/455; H03L7/06; H03L7/093; H03L7/095; H04L7/00; H04L27/227; H04L27/38; (IPC1-7): H04L27/227; H03L7/06; H03L7/093; H03L7/095; H04L7/00; H04L27/38
Domestic Patent References:
| JP2000174835A |
Attorney, Agent or Firm:
Nobuhiro Funatsu
Kiyotaka Sakamoto
Kiyotaka Sakamoto