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Patent Searching and Data


Title:
DIGITAL SELF-CORRECTING SYSTEM FOR ANALOG-TO-DIGITAL CONVERTER CONNECTED TO PIPELINE
Document Type and Number:
Japanese Patent JPH11274927
Kind Code:
A
Abstract:

To correct at the same time the errors of both a capacitor and an amplifier by showing a method for proving that the errors which are caused by the mismatching rate and nonlinearity of the capacitor and the gain and nonlinearity of the amplifier can be eliminated at the same time and effectively.

A digital approximate bit of Vin is decomposed at each stage of a converter. A 1st stage 702 receives a sampled voltage Vin as its input and produces the digital output of a single bit and an output voltage V0. The voltage V0 becomes Vin with respect to a next stage 704, and the digital output D1 functions as a digital input D2 with respect to the stage 704. Meanwhile, the digital output of each stage is also inputted to a digital logic unit 710 for a self-correcting digital approximate output 716 of the input voltage. The 2nd and its consecutive stages of the converter receive the Vin and D1 as their inputs and have the V0 and D1 for the unit 710 and for the next stage (i+1).


Inventors:
NAGARAJ KRISHNASWAMY
Application Number:
JP988299A
Publication Date:
October 08, 1999
Filing Date:
January 18, 1999
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H03M1/14; H03M1/10; H03M1/44; H03M1/16; (IPC1-7): H03M1/14; H03M1/44
Attorney, Agent or Firm:
Akira Asamura (3 outside)