PURPOSE: To obtain a circuit corresponding to the 16-bit mode and the 12-bit mode with a comparatively small scale by using a shift register required also for the 16-bit mode in common with the compression of the 12-bit mode.

CONSTITUTION: The circuit consists of a shift register 1 converting serially a 1-word 16-bit parallel data, a data conversion circuit 2 generating a 4-bit from a high-order 8-bit in a 16-bit data and a shift control circuit 7 controlling the shift clock of the shift register 1. In case of the 16-bit mode, the data of the shift register 1 is outputted as it is and in case of the 12-bit mode, after the 16-bit data is shifted so that the highest-order bit among bits different from the most significant bit comes to specific bit location of the shift register 1, the 4-bit of the output of the data conversion circuit 2 and a prescribed 8-bit of the shift register 1 are synthesized to generate and output the 12-bit data. Thus, a circuit corresponding to both the 16-bit and 12-bit modes is obtained with a comparatively small circuit scale.