PURPOSE: To suppress jitter of a timing clock in two=wire full duplex transmission by storing frequency control information obtained from the phase comparison during the reception burst period and using the frequency control information for frequency control during transmission burst period.

CONSTITUTION: A phase comparator circuit 1 compares the phase of a reception signal 2 with the phase of a clock signal 3 during the reception burst period, its output is smoothed by a smoothing circuit 4 and given to a memory circuit 6 and a selector 7 as frequency control information 5. A variable frequency divider 9 is controlled by the output of a selector 7 and the master clock from the master clock circuit 8 is given to a counter 10 via a variable frequency divider 9 and the output of the counter 10 is led as the clock signal 3. The frequency control information stroed in the memory circuit 6 is read at random during the transmission burst period and given to the variable frequency divider 9 via the selector 7.