Title:
SEMICONDUCTOR DEVICE WITH INSULTED GATE BIPOLAR TRANSISTOR
Document Type and Number:
Japanese Patent JP3209091
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device with an insulated gate bipolar transistor having a high breakdown voltage at latch-up and operated with a low on-voltage at a normal state.
SOLUTION: An IGBT semiconductor structure includes a p+-type deep well-shaped main emitter region 7a formed on a conductivity modulation layer 4, a p-type outer junction emitter region 7b at an outer adjoining position to a face-side shallow part at the well edge of the main emitter region 7a, an n-type shallow source region 9A on a face of the outer junction emitter region 7b, and an n+-type source/contact region 9B formed on the main emitter region 7a in a position adjoining to the n-type source region 9A. In this way an n+-type source layer 9 is made up of two parts, namely the low-density source region 9A with a limited scale and the high-density source/ contact region 9B put in ohmic contact with an emitter electrode 8. Since the source region 9A is low-density n-type, a current amplification factor hFE is made low to increase latch-up withstanding value. In addition, the n+-type source/contact region 9B is continuously formed to the n-type source region 9A, so the contact resistance is almost always kept to a low value and a low ion voltage is obtained constantly.
Inventors:
Masato Ohtsuki
Ryu Saito
Yasuhiko Ohnishi
Ryu Saito
Yasuhiko Ohnishi
Application Number:
JP13680196A
Publication Date:
September 17, 2001
Filing Date:
May 30, 1996
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L29/78; H01L29/06; H01L29/10; H01L29/739; (IPC1-7): H01L29/78
Domestic Patent References:
| JP4196174A | ||||
| JP6384164A | ||||
| JP2162742A | ||||
| JP8186254A |
Attorney, Agent or Firm:
Minoru Yamada